The article describes an overflow situation with the cookie FIFO (First-In, First-Out) buffer that is used by the ASIC within the FPC and PIC.

The below could be observed in the syslog messages followed by a FPC crash:

[Feb 26 01:03:00.312 LOG: Debug] precl_cmalarm_info_create: idx 1 for fpc X pic y aisc-id 95 asic-inst 0 pg 0 from config idx 3 error 0x340005 level 1 threshold 1 PRECL_CMERROR_COOKIE_FIFO_OVERFLOW

The log shows an FPC and PIC error. This specific error pertains to an overflow scenario of the cookie FIFO buffer handled by the ASIC.

It signifies that there was an overflow of the cookie FIFO buffer. FIFO (First-In, First-Out) is one of the forms of data queue employed by the system to hold packets and metadata. A cookie FIFO overflow means that this buffer was filled above its capacity.

This type of error may be caused by:

• Excessive traffic volume that overloads the buffer.
• Hardware resource depletion in which the FPC or ASIC is unable to process the amount of data passing through.
• Possible hardware malfunction in the ASIC or FPC that is filling the buffer improperly or too rapidly.

To resolve the issue, need to follow the below steps:

a. Check the health of the FPC/PIC.

show chassis fpc

show chassis pic

show chassis environment

b. Examine system logs for additional errors. Check the below log:

show log messages

c. Heavy traffic levels may overflow buffers. Look for heavy traffic on the router or network load above normal levels.

d. Look for any excessive ACLs, filters, or other items that may be putting a burden on the system's packet-handling capability.

e. Monitor memory and CPU usage to see if the router is resource-starved:

If the problem continues or hardware failure is suspected, it is advised to contact Juniper Support for further diagnosis and possible replacement of failed hardware.