Description

This article explains one of the reasons why a port is getting auto-channelized on EX4600, QFX5100, and QFX5200 switches, and provides workaround for the same.

Symptoms

1) It was reported that after the device upgrade, one et- interface keeps reverting to 4x10 xe- ports instead of et port. All other et- interfaces with same QSFP+ optic remains the same without getting converted.

2) When checking the Chassisd logs, found that the specific interface is auto-channelized and gets converted to xe- ports:

Dec 15 17:34:21  auto-chan: sending the global auto-channelization 0 flag to pfe 
Dec 15 17:34:21 CHASSISD_PARSE_COMPLETE: Using new configuration
Dec 15 17:35:29  pic_update_port_range Deleting IFD: et-0/0/15
Dec 15 17:35:29  ifdev_detach_port(et-0/0/15)
Dec 15 17:35:29  ifd et-0/0/15 marked as gone
Dec 15 17:35:29  PIC (fpc 0 pic 0) message operation: change. ifd count 53, flags 0x3 in mesg
Dec 15 17:35:32  pic_copy_port_info:Got SFP Rev=REV 01, Pno=740-060378, Sno=1FCM422700Y    
Dec 15 17:35:32  pic_copy_port_info:Got SFP Rev=REV 01, Pno=740-060378, Sno=1FCM422600E    
Dec 15 17:35:32  create_pic_entry: pic i2c 0xf0ac, hw qs 12 supported qs 12, flags 0x0, pic port 15, speed 10000000000            
Dec 15 17:35:32  xe-0/0/15:0 ifm_channel: 0x0, ifm_fe = 0, local_dev_id:0, global_dev_id:0, port_num:73
Dec 15 17:35:32  capability: xe-0/0/18:0, cap flag = 43072, media: 2 porttype 27
Dec 15 17:35:32  ifdev_create entered xe-0/0/15:0
Dec 15 17:35:32  xe-0/0/15:0: large delay buffer cleared
Dec 15 17:35:32  fpc_is_synce_cap: FPC i2c: 0xbce, PIC type: 0xf0ac
Dec 15 17:35:32  pic_update_ifdev_tlvs: xe-0/0/15:0 Not SyncE capable
Dec 15 17:35:32  pic_update_ifdev_tlvs: xe-0/0/15:0 IFM type is Ether, SyncE TLV is added
Dec 15 17:35:32  create_pic_entry: pic i2c 0xf0ac, hw qs 12 supported qs 12, flags 0x0, pic port 15, speed 10000000000      
Dec 15 17:35:32  xe-0/0/15:1 ifm_channel: 0x1, ifm_fe = 0, local_dev_id:0, global_dev_id:0, port_num:73
Dec 15 17:35:32  capability: xe-0/0/18:1, cap flag = 43072, media: 2 porttype 27
Dec 15 17:35:32  ifdev_create entered xe-0/0/15:1
Dec 15 17:35:32  xe-0/0/15:1: large delay buffer cleared
Dec 15 17:35:32  fpc_is_synce_cap: FPC i2c: 0xbce, PIC type: 0xf0ac
Dec 15 17:35:32  pic_update_ifdev_tlvs: xe-0/0/15:1 Not SyncE capable
Dec 15 17:35:32  pic_update_ifdev_tlvs: xe-0/0/15:1 IFM type is Ether, SyncE TLV is added
Dec 15 17:35:32  create_pic_entry: pic i2c 0xf0ac, hw qs 12 supported qs 12, flags 0x0, pic port 15, speed 10000000000
Dec 15 17:35:32  xe-0/0/15:2 ifm_channel: 0x2, ifm_fe = 0, local_dev_id:0, global_dev_id:0, port_num:73
Dec 15 17:35:32  capability: xe-0/0/15:2, cap flag = 43072, media: 2 porttype 27
Dec 15 17:35:32  ifdev_create entered xe-0/0/15:2
Dec 15 17:35:32  xe-0/0/15:2: large delay buffer cleared
Dec 15 17:35:32  fpc_is_synce_cap: FPC i2c: 0xbce, PIC type: 0xf0ac
Dec 15 17:35:32  pic_update_ifdev_tlvs: xe-0/0/15:2 Not SyncE capable
Dec 15 17:35:32  pic_update_ifdev_tlvs: xe-0/0/15:2 IFM type is Ether, SyncE TLV is added
Dec 15 17:35:32  create_pic_entry: pic i2c 0xf0ac, hw qs 12 supported qs 12, flags 0x0, pic port 15, speed 10000000000
Dec 15 17:35:32  xe-0/0/15:3 ifm_channel: 0x3, ifm_fe = 0, local_dev_id:0, global_dev_id:0, port_num:73
Dec 15 17:35:32  capability: xe-0/0/15:3, cap flag = 43072, media: 2 porttype 27
Dec 15 17:35:32  ifdev_create entered xe-0/0/15:3
Dec 15 17:35:32  xe-0/0/15:3: large delay buffer cleared
Dec 15 17:35:32  fpc_is_synce_cap: FPC i2c: 0xbce, PIC type: 0xf0ac
Dec 15 17:35:32  pic_update_ifdev_tlvs: xe-0/0/15:3 Not SyncE capable
Dec 15 17:35:32  pic_update_ifdev_tlvs: xe-0/0/15:3 IFM type is Ether, SyncE TLV is added
Dec 15 17:35:32  create_pic_entry: pic i2c 0xf0ac, hw qs 12 supported qs 12, flags 0x0, pic port 15, speed 10000000000

3) Interfaces gets auto-channelized and converted into xe- ports:

{master:0}[edit]
user@QFX10K# run show interfaces terse | match "xe-0/0/15"
xe-0/0/15:0             up    up
xe-0/0/15:1             up    up
xe-0/0/15:2             up    up
xe-0/0/15:3             up    up

Solution

Since auto-channelization is enabled by default on EX4600, QFX5100, and QFX5200 series of switches, the 40-Gbps QSFP+ ports are channelized automatically (auto-channelized) if any of the four channels on the 40-Gbps QSFP+ port receive data, unless channelization is configured either at the chassis level or at the port level. 

1) Try swapping the port to see if the other port is also getting auto-channelized. If yes, this will confirm that the port is receiving some information/signal from the peer end due to which it is getting auto-channelized into 4 xe- ports,

(a) inorder to match some physical parameter (speed, duplex etc.) with the peer end.
                                                     (or)
(b) It could be due to some physical issues at the peer end (like optic, cabling etc).

Note: When you try reverting the port back to et- by disabling auto-channelization with the command: 'disable-auto-speed-detection', you will notice that the et- port status goes physically down indicating Layer-1 issues.

2) Hence, Clean/Reseat and Replace optics at the peer end. Check cablings as well.
It is always recommended to check the optics/cablings at both the ends.
 

Modification History

2024-08-06 : Article Created