Description

Clock failure from Zarlink chip on the control board of the current master RE causes GRES switchover. Interfaces can go down due to this issue.

Symptoms

Clock failure from Zarlink chip on the control board can be identified by the following syslog message:

Apr 20 22:44:48.706 2024 router-re0 chassisd[10766]: %DAEMON-3-CHASSISD_CB_19MHZ_CLK_FAIL: Mastership switching over due to CB 0 19.44MHz clock failure

This is the clock that is based on the zarlink on CB generates and will be used by the line cards. This clock is monitored periodically. The failure of such clock signal is a critical event and GRES should be performed.

Solution

Such clock failure can cause interfaces going down because the correct clocking from CB is critical for correct FPC operation. The affected interfaces should recover after GRES.

Modification History

2024-06-20 : Article Created