Chassis alarm with 'FPC <no> Memory corrected error' may be seen on device.
JTAC> show chassis alarms
1 alarms currently active
Alarm time Class Description
2024-06-02 11:52:58 +03 Minor FPC 14 Memory corrected error
Below logs can be seen in messages:
Jun 2 11:52:56.631 JTAC-fpc14 mcelog[13944]: warning: 8 bytes ignored in each record
Jun 2 11:52:56.631 JTAC-fpc14 kernel: mce: [Hardware Error]: Machine check events logged
Jun 2 11:52:56.631 JTAC-fpc14 kernel: EDAC sbridge MC0: HANDLING MCE MEMORY ERROR
Jun 2 11:52:56.631 JTAC-fpc14 kernel: EDAC sbridge MC0: CPU 0: Machine Check Event: 0 Bank 7: 8c00004000010090
Jun 2 11:52:56.631 JTAC-fpc14 kernel: EDAC sbridge MC0: TSC 224471cd1ae0d
Jun 2 11:52:56.631 JTAC-fpc14 kernel: EDAC sbridge MC0: ADDR 6f665aa00
Jun 2 11:52:56.631 JTAC-fpc14 kernel: EDAC sbridge MC0: MISC 1503e3e86
Jun 2 11:52:56.631 JTAC-fpc14 kernel: EDAC sbridge MC0: PROCESSOR 0:50663 TIME 1717318376 SOCKET 0 APIC 0
Jun 2 11:52:56.631 JTAC-fpc14 kernel: EDAC DEBUG: get_memory_error_data: SAD interleave package: 4 = CPU socket 0, HA 0, shiftup: 1
Jun 2 11:52:56.631 JTAC-fpc14 kernel: EDAC DEBUG: get_memory_error_data: TAD#1: address 0x00000006f665aa00 < 0x000000087fffffff, socket interleave 0, channel interleave 2 (offset 0x80000000), index 0, base ch: 0, ch mask: 0x01
Jun 2 11:52:56.631 JTAC-fpc14 kernel: EDAC DEBUG: get_memory_error_data: RIR#0, limit: 15.999 GB (0x00000003ffffffff), way: 2
Jun 2 11:52:56.631 JTAC-fpc14 kernel: EDAC DEBUG: get_memory_error_data: RIR#0: channel address 0x33b32d500 < 0x3ffffffff, RIR interleave 1, index 0
Jun 2 11:52:56.631 JTAC-fpc14 kernel: EDAC DEBUG: sbridge_mce_output_error: area:DRAM err_code:0001:0090 socket:0 ha:0 channel_mask:1 rank:0
Jun 2 11:52:56.631 JTAC-fpc14 kernel: EDAC MC0: 1 CE memory read error on CPU_SrcID#0_Ha#0_Chan#0_DIMM#0 (channel:0 slot:0 page:0x6f665a offset:0xa00 grain:32 syndrome:0x0 - area:DRAM err_code:0001:0090 socket:0 ha:0 channel_mask:1 rank:0)
This “FPC <no> Memory corrected error" alarm is caused by a memory error that has been detected in CPU DRAM memory bank.
For DIMM#0: DIMM stands for Dual In-line Memory Module.
This is due to a single-bit error, which is detected and corrected by the system's error checking & correction (ECC) mechanism.
In most case, the alarm clears on its own & it is suggested to monitor the FPC for the next 24-48 hours for its stability.
If the alarm is not cleared on its own, we can follow the steps below:
clear chassis fpc errors fpc-slot <slot> all
If the alarm appears again after reboot, then please contact JTAC for further assistance. FPC may need to be replaced.
2025-07-31 : Minor updated
2024-06-02 : Article Created