This Major Alarm may be seen for the following DPCE (Dense Port Concentrator - Enhanced) model type installed in MX routers:
FPC 0 REV 27 750-020452 AA1111 DPCE 40x 1GE X EQ
ID: DPCE 40x 1GE X EQ FRU Model Number: DPCE-X-Q-40GE-SFP
During network operations, the DPCE 40x 1GE X EQ FPC may encounter a Major alarm "I Chip Error code: 0x150010". An example is below:
May 25 14:30:56 send: red alarm clear, device FPC 0, reason FPC 0 Major Errors - I Chip Error code: 0x150010 May 25 14:30:58 send: red alarm set, device FPC 0, reason FPC 0 Major Errors - I Chip Error code: 0x150010 May 25 14:30:58 send: red alarm clear, device FPC 0, reason FPC 0 Major Errors - I Chip Error code: 0x150010 ........ May 25 15:44:11 send: red alarm clear, device FPC 0, reason FPC 0 Major Errors - I Chip Error code: 0x150010 May 25 15:44:13 send: red alarm set, device FPC 0, reason FPC 0 Major Errors - I Chip Error code: 0x150010
clear - set - clear
The error code is a transient ECC/CRC (error checking and correction / cyclic redundancy check) process error that goes into a set, clear, and set pattern. Log messages like the following may be seen:
May 29 09:04:40 mx960 fpc0 ICHIP(0): multiple uncorrectable ECC errors, count 65535 May 29 09:04:42 mx960 fpc0 ICHIP(0): multiple uncorrectable ECC errors, count 65535 May 29 09:04:44 mx960 fpc0 ICHIP(0): multiple correctable ECC errors, count 65535 May 29 09:04:45 mx960 fpc0 ICHIP(0): multiple uncorrectable ECC errors, count 65535 May 29 09:04:47 mx960 fpc0 ICHIP(0): multiple uncorrectable ECC errors, count 65535 May 29 09:04:49 mx960 fpc0 ICHIP(0): multiple uncorrectable ECC errors, count 65535 May 29 09:04:07 mx960 fpc0 Cmerror Op Set: I Chip: ICHIP(0) ICHIP packet crc error at IP/LSIF interface May 29 09:04:09 mx960 fpc0 Cmerror Op Set: I Chip: ICHIP(0) ICHIP packet crc error at IP/LSIF interface May 29 09:04:11 mx960 fpc0 Cmerror Op Set: I Chip: ICHIP(0) ICHIP packet crc error at IP/LSIF interface