This article explains the meaning of the following syslog message and indicates the steps to overcome it.
fpcx INTR: throttle 60sec TLCHIP[1]:tl.edf.intr.status:page_mem_prog_err(0)
Syslog Message:
user@host> show log messages | match INTR: May 30 06:33:16 fpc3 INTR: throttle 30sec TLCHIP[1]:tl.edf.intr.status:page_mem_prog_err(0): (Count:40) Jun 1 02:04:33 fpc0 INTR: throttle 30sec TLCHIP[2]:tl.edf.intr.status:page_mem_prog_err(0): (Count:78)
Detailed Syslogs triggered on an FPC:
user@host> show log messages |match fpc5 Sep 1 20:58:56 fpc5 INTR: throttle 60sec TLCHIP[0]:tl.edf.intr.status:page_mem_prog_err(0): (Count:1) <-- Check the TLCHIP Is on which error is seen. Here, it is TLCHIP 0 Sep 2 08:15:01 fpc5 INTR: throttle 90sec TLCHIP[0]:tl.edf.intr.status:page_mem_prog_err(0): (Count:3) Sep 2 09:57:24 fpc5 INTR: throttle 120sec TLCHIP[0]:tl.edf.intr.status:page_mem_prog_err(0): (Count:5) Sep 2 11:45:20 fpc5 INTR: throttle 90sec TLCHIP[0]:tl.edf.intr.status:page_mem_prog_err(0): (Count:6) Sep 3 05:30:21 fpc5 INTR: throttle 60sec TLCHIP[0]:tl.edf.intr.status:page_mem_prog_err(0): (Count:7) Sep 3 08:47:02 fpc5 INTR: throttle 90sec TLCHIP[0]:tl.edf.intr.status:page_mem_prog_err(0): (Count:9) Sep 3 10:28:11 fpc5 INTR: throttle 120sec TLCHIP[0]:tl.edf.intr.status:page_mem_prog_err(0): (Count:11) Sep 3 12:07:31 fpc5 INTR: throttle 90sec TLCHIP[0]:tl.edf.intr.status:page_mem_prog_err(0): (Count:12) Sep 3 12:38:17 fpc5 INTR: throttle 60sec TLCHIP[0]:tl.edf.intr.status:page_mem_prog_err(0): (Count:13) Sep 3 13:04:46 fpc5 INTR: throttle 30sec TLCHIP[0]:tl.edf.intr.status:page_mem_prog_err(0): (Count:14) Sep 3 15:18:07 fpc5 INTR: throttle 60sec TLCHIP[0]:tl.edf.intr.status:page_mem_prog_err(0): (Count:16) Sep 3 22:58:11 fpc5 INTR: throttle 30sec TLCHIP[0]:tl.edf.intr.status:page_mem_prog_err(0): (Count:17) Sep 3 23:28:35 fpc5 INTR: throttle 60sec TLCHIP[0]:tl.edf.intr.status:page_mem_prog_err(0): (Count:18) <-- Count keeps increasing when each error is triggered
<-- Count keeps increasing when each error is triggered
Egress Descriptor Fetch, EDF accesses descriptor based on next-hop provided by the ingress, calculates L2 and L3 length needed by counters and policers' L3 MTU check. The logs are cosmetic in nature and does not impact any services.
Check if there is any impact/active alarm matching the timestamp of this error. In case there is any impact/ Active alarm, contact JTAC for detailed analysis.
If the frequency of the alarm is low and does not log continuously, you can choose to ignore the message.
If you want to get rid of the error, restart the FPC.
user@host> request chassis fpc slot 5 offline <wait for 2 minutes> [MASTER] user@host> request chassis fpc slot 5 online
OR [MASTER] @pl-ktw01a-rc1> request chassis fpc slot 5 restart
[MASTER] @pl-ktw01a-rc1> request chassis fpc slot 5 restart
For JTAC analysis, please collect the logs below from FPC 5:
user@host> request execute pfe command "show nvram" target fpc5
user@host> request execute pfe command "show syslog messages" target fpc5
user@host> request execute pfe command "show tlchip 0 intr_counts all" target fpc5 <-- For TLCHIP 0
Example:
tl.edf.intr.status page_mem_prog_err(0) : 18 <-- Gives the count of error
user@host> request execute pfe command "show tlchip 1 intr_counts all" target fpc5 <-- For TLCHIP 1
user@host> request execute pfe command "show tlchip 0 edf config trapcodes" target fpc5
user@host> request execute pfe command "show tlchip 1 edf config trapcodes" target fpc5
user@host> request execute pfe command "show tlchip 0 edf stats periodic" target fpc5
user@host> request execute pfe command "show tlchip 1 edf stats periodic" target fpc5
user@host> request execute pfe command "bringup jspec read tlchip[0] register edf intr status" target fpc5
user@host> request execute pfe command "bringup jspec read tlchip[1] register edf intr status" target fpc5