Description

In order to prioritize traffic in the network receiving certain TOS bits and take the GRE tunnel, it is required to apply the scheduler to the gr- interface.

This article explains how to apply schedulers to gr- interface.

Solution

Check the index number for gr-interface:

user2@mx480> show interfaces gr-3/2/0 
Physical interface: gr-3/2/0, Enabled, Physical link is Up
  Interface index: 212, SNMP ifIndex: 823
  Type: GRE, Link-level type: GRE, MTU: Unlimited, Speed: 10000mbps
  Device flags   : Present Running
  Interface flags: Point-To-Point SNMP-Traps
  Input rate     : 0 bps (0 pps)
  Output rate    : 0 bps (0 pps)

By default, the IFD of GRE tunnel reserves BW only for queue 0-3, exhausting queue 4-7 as shown below:

user2@mx480> start shell pfe network fpc3

RTR3(mx480 vty)# show cos halp ifd 212
--------------------------------------------------------------------------------
IFD name: gr-3/2/0   (Index 212)
    XM chip id: 0
    XM chip Scheduler: 0
    XM chip L1 index: 0
    XM chip dummy L2 index: 0
    XM chip base Q index: 0
    Number of queues: 8
    Rich queuing support: 0 (ifl queued:0)
----------------------------------------------------------------------------------------
Queue  State        Max           Guaranteed    Burst   Weight  G-Pri  E-Pri  WRED  TAIL
Index               Rate          Rate          Size                          Rule  Rule
----------------------------------------------------------------------------------------
0      Configured   10000000000   2500000000    131064  31      GL     EL     4     112 
1      Configured   10000000000   2500000000    131064  31      GL     EL     4     112 
2      Configured   10000000000   2500000000    131064  31      GL     EL     4     112 
3      Configured   10000000000   2500000000    131064  31      GL     EL     4     112 
4      Configured   10000000000   0             131064  1       GL     EL     0     1   
5      Configured   10000000000   0             131064  1       GL     EL     0     1   
6      Configured   10000000000   0             131064  1       GL     EL     0     1   
7      Configured   10000000000   0             131064  1       GL     EL     0     1   
----------------------------------------------------------------------------------------

In order to avoid queue drops for traffic using queue 4-7, apply the scheduler to the GRE interface under COS configuration as shown in the example below:

user1@mx480> show configuration class-of-service schedulers  
SC-NC {
    transmit-rate percent 5;
    buffer-size percent 5;
    priority high;
}
SC-EF {
    transmit-rate percent 20;
    buffer-size percent 20;
    priority high;
}
SC-AF41 {
    transmit-rate percent 25;
    buffer-size percent 25;
    priority low;
}
SC-AF31-CS3 {
    transmit-rate percent 15;
    buffer-size percent 15;
    priority low;
}
SC-AF21 {
    transmit-rate percent 25;
    buffer-size percent 25;
    priority low;
}
SC-AF11 {
    transmit-rate percent 1;
    buffer-size percent 1;
    priority low;
    drop-profile-map loss-priority low protocol any drop-profile DP-RED;
}
SC-BE {
    transmit-rate percent 9;
    buffer-size percent 9;
    priority low;
    drop-profile-map loss-priority low protocol any drop-profile DP-RED;
}                                       


user2@mx480> show configuration class-of-service scheduler-maps 

SM-SCHED {
    forwarding-class ef scheduler SC-EF;
    forwarding-class af41 scheduler SC-AF41;
    forwarding-class af31-cs3 scheduler SC-AF31-CS3;
    forwarding-class af21 scheduler SC-AF21;
    forwarding-class af11 scheduler SC-AF11;
    forwarding-class best-effort scheduler SC-BE;
    forwarding-class network-control scheduler SC-NC;
}

[MASTER]
user1@mx480> show configuration class-of-service interfaces 
gr-3/2/0 {
    scheduler-map SM-SCHED;
}

RTR3(test-1mx480 vty)# show cos halp ifd 212
--------------------------------------------------------------------------------
IFD name: gr-3/2/0   (Index 212)
    XM chip id: 0
    XM chip Scheduler: 0
    XM chip L1 index: 0
    XM chip dummy L2 index: 0
    XM chip base Q index: 0
    Number of queues: 8
    Rich queuing support: 0 (ifl queued:0)
----------------------------------------------------------------------------------------
Queue  State        Max           Guaranteed    Burst   Weight  G-Pri  E-Pri  WRED  TAIL
Index               Rate          Rate          Size                          Rule  Rule
----------------------------------------------------------------------------------------
0      Configured   10000000000   900000000     131064  11      GL     EL     5     88  
1      Configured   10000000000   2000000000    131064  25      GH     EH     4     106 
2      Configured   10000000000   100000000     131064  1       GL     EL     5     34  
3      Configured   10000000000   500000000     131064  6       GH     EH     4     72  
4      Configured   10000000000   2500000000    131064  31      GL     EL     4     112 
5      Configured   10000000000   1500000000    131064  18      GL     EL     4     99  
6      Configured   10000000000   2500000000    131064  31      GL     EL     4     112 
7      Configured   10000000000   0             131064  1       GL     EL     0     1   
----------------------------------------------------------------------------------------

Modification History

2020-02-24: minor non-technical edits.