Description

This article describes the issue of commit not generating an error, when a scheduler map is configured via the group, with more than one scheduler configured as strict-high , high , or medium-high on the IQ2 PIC interface.


Symptoms

Gigabit Ethernet IQ2 PICs support only one queue in the scheduler map, with either the medium-high , high , or strict-high priority. If more than one queue is configured with the high or strict-high priority, the one that appears first in the configuration is implemented with the strict-high priority.

This queue receives unlimited transmission bandwidth. The remaining queues are implemented as low priority, which means that they might be starved. Commit does not generate an error, when a scheduler-map is applied via group to all interfaces, with more than one scheduler configured as strict-high , high , or medium-high on the IQ2 PIC interface.
 
For example:

set groups IQ2-2PRI-QUEUE class-of-service interfaces <*> scheduler-map IQ2-2PRI-QUEUE
set class-of-service scheduler-maps IQ2-2PRI-QUEUE forwarding-class network-control scheduler network-control
set class-of-service scheduler-maps IQ2-2PRI-QUEUE forwarding-class expedited-forwarding scheduler expedited-forwarding
set class-of-service scheduler-maps IQ2-2PRI-QUEUE forwarding-class best-effort scheduler best-effort
set class-of-service scheduler-maps IQ2-2PRI-QUEUE forwarding-class assured-forwarding scheduler assured-forwarding

set class-of-service schedulers network-control transmit-rate percent 5
set class-of-service schedulers network-control buffer-size percent 5
set class-of-service schedulers network-control priority high
set class-of-service schedulers expedited-forwarding transmit-rate percent 20
set class-of-service schedulers expedited-forwarding buffer-size percent 20
set class-of-service schedulers expedited-forwarding priority medium-high
set class-of-service schedulers best-effort transmit-rate remainder
set class-of-service schedulers best-effort buffer-size remainder
set class-of-service schedulers best-effort priority medium-low
set class-of-service schedulers assured-forwarding transmit-rate percent 1
set class-of-service schedulers assured-forwarding buffer-size percent 1
set class-of-service schedulers assured-forwarding priority low

Step 1 :

Applying a scheduler-map via group to an individual interface in IQ2 PIC, with more than one scheduler configured as strict-high , high , or medium-high :
lab@iridium-RE0#set class-of-service interfaces ge-0/1/0 apply-groups IQ2-2PRI-QUEUE
lab@iridium-RE0# commit
[edit class-of-service interfaces]
'ge-0/1/0'
More than one scheduler is configured as strict-high , high , or medium-high in bisht for ge-0/1/0 . IFD ge-0/1/0 supports only one scheduler with strict-high , high , or medium-high .
error: configuration check-out failed
The commit check fails, as it checks the PIC type.

Step 2 :

Applying a scheduler-map via group to all interfaces, with more than one scheduler configured as strict-high , high , or medium-high :
lab@iridium-RE0# set class-of-service interfaces all apply-groups IQ2-2PRI-QUEUE

[edit]
lab@iridium-RE0# commit
May 18 07:29:07 iridium-RE0 mgd[1421]: UI_COMMIT: User 'lab' requested 'commit' operation (comment: none)
May 18 07:29:08 iridium-RE0 ffp[1607]: "dynamic-profiles": No change to profiles
commit complete

Solution

The commit validation passes, as the PIC type is not checked, when the scheduler-map is applied to all interfaces via the group configuration.

This is expected behavior. Even though commit validation succeeds on one queue, which appears first in the configuration, it is implemented with the strict-high priority. The remaining queues are implemented as low priority. This can be verified by looking at the log messages, which are generated, when committing the configuration.

The following example is of log messages generated during commit:

[edit]
lab@iridium-RE0#

May 18 07:29:09 iridium-RE0 (FPC Slot 0, PIC Slot 1) Only one queue with priority is allowed in IQ2 platform. Will configure 1 q_num for ge-0/1/0 -1 as high priority and ignore high priority setting of 3 queue
May 18 07:29:09 iridium-RE0 (FPC Slot 0, PIC Slot 1) Only one queue with priority is allowed in IQ2 platform. Will configure 1 q_num for ge-0/1/1 -1 as high priority and ignore high priority setting of 3 queue
May 18 07:29:09 iridium-RE0 (FPC Slot 0, PIC Slot 1) Only one queue with priority is allowed in IQ2 platform. Will configure 1 q_num for ge-0/1/2 -1 as high priority and ignore high priority setting of 3 queue

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