Description

When migrating CTPOS from 5.x to 6.0R1 with a new style processor card (PP332), the upgrade could hang and not finish the reboot process.

Symptoms

This failure occurs if you use the wrong memory module for your processor type. There are two CTP2000 upgrade kits available, depending on the type of processor card you have in your CTP.  The 1Gb memory modules in the kits are specific to the type of processor and they are not compatible with each other. Before upgrading to version 6.0 make sure your kit is compatible with your processor type, they are referred to as "PP310" (older style processor) and "PP332" (newer style processor).   

The upgrade document  Juniper Networks CTP2000 Circuit to Packet Platform  provides further details on how to identify your processor as well as guide you through the upgrade process. 

A sample console output of the failure, during the boot process, is shown:

kernel /bzImage-2.4.29 ro root=LABEL=CTP_ROOT console=ttyS0,9600n8                
 [Linux-bzImage, setup=0xc00, size=0x104655]          
 initrd /initrd-2.4.29.img                 
 [Linux-initrd @ 0x37e20000, 0x1cffff bytes]

**** ****
**** ****          
**** Modified system for CTP_2000 serial support.
**** Console changes will take place at next reboot.
**** ****
**** ****

Solution

If a non-ECC 1Gb memory module is used in error, as part of the version 6.0 upgrade on a PP332 processor, then the CTP will hang when rebooting. The PP332 processor requires a 1Gb ECC memory module whereas the PP310 processor requires a non-ECC memory module.

To tell whether the memory is ECC or Non-ECC:

  • Look for a sticker on the memory module indicating whether it is ECC or non-ECC.
  • If no sticker exists visually, inspect the memory chips themselves. Compare your 1Gb memory module against the image provided to verify ECC and non-ECC types:
alt

For 1Gb chips: 
  • Non-ECC 1Gb - missing a chip in the center on both sides
  • ECC - no chips are missing on either side
For 512M chips:
  • Non-ECC: Two rows of chips on both sides.
    • Top row has chips aligned vertically with no missing chips on either side.
    • Bottom row chips are aligned horizontally with missing chip in center on both sides.
  • ECC: One row of chips both sides.
    • One side has a missing chip in center
    • Other side no missing chips.
    • Also, no space between individual chips as all chips are as close as they possibly can be to each other.

Modification History


2024-08-07: Archiving this as a part of EOS Policy