Description

We have a device where PTP CLOCK that suddenly went HOLDOVER

Symptoms

Apr 16 17:04:49.287 2026 Router: %PFE-3: fpc10 ptp_fpga_ppe_packet_tx PTP FPGA: No TX FIFO space available to send pkt of 16 words, 15 available

Apr 16 17:04:49.287 2026 Router: %PFE-3: fpc10 PTP FPGA: Hash Collision for key 00000168, 0000000000000000 hash_value 183

Apr 16 17:04:50.007 2026 Router: %PFE-3: fpc10 Resetting the Playback Engine

Apr 16 17:04:52.088 2026 Router: %PFE-3: fpc10 Resetting the Playback Engine

Solution

From the available information, this looks to be PR 1771889 (internal).

 

RCA from PR:

Issue in PTP FPGA image where it automatically reset FPGA when both Hybrid & PTP clocks went LOL.

This may happen during clock mode changes between Hybrid to plain PTP.

 

Detectability:

Logs show Err Resetting the Playback Engine messages

 

Workaround:

Restart FPC

 

Fixed in:

24.2R2, 24.4R1 & all above releases.

 

Regarding the TX FIFO logs, this is why I am stating that it’s because of the underlying HW issue, the ptp might have gone down. But we do not know what exact issue happened then.

Pls refer below PR/KB, where it clearly state this is a HW issue & solution is to restart or replace if not fixed by restart.

PR1743065/KB71728 [juniper.net]

Modification History

2026-07-09 : Article Created