The PS0 interface, which has anchor point on FPC0, is not learning arp after upgrade due to which 3 BGP peers fail to come up.
The issue gets resolved when anchor point for PS interface is moved to FPC11 or when the lt-0/2/0 is deleted & recreated.
Both FPCs are MPC2E.
lt-0/2/0 {
hierarchical-scheduler maximum-hierarchy-levels 2;
}
We observed that ‘flexible-queuing-mode’ knob is needed under chassis, when HQoS is enabled for mpc2e FPC.
With flexible-queueing-mode enabled
PFE:?NGMPC2(indore vty)# show cos scheduler-hierarchy
class-of-service egress scheduler hierarchy - rates in kbps
-------------------------------------------------------------------------------------
shaping guarntd delaybf excess
interface name index rate rate rate rate other
---------------------------- --------- ------- ------- ------- ------- -------------
pd-2/0/0 172 0 0 0 0
q 0 - pri 0/1 4 0 25% 25% 0
q 1 - pri 0/1 4 0 25% 25% 0
q 2 - pri 0/1 4 0 25% 25% 0
q 3 - pri 0/1 4 0 25% 25% 0
<snip>
lt-2/0/0 204 0 0 0 0
lt-2/0/0-rtp 204 10000000 0 10000000 0
q 0 - pri 0/1 2 0 95% 95% 0
q 3 - pri 0/1 2 0 5% 5% 0
NGMPC2(indore vty)# show cos halp ifd 204
--------------------------------------------------------------------------------
rich queueing enabled: 0
Q chip present: 0
IFD name: lt-2/0/0 (Index 204) egress information
XM chip id: 0
XM : chip Scheduler: 0
XM chip L1 index: 11
XM chip dummy L2 index: 22
XM chip base Q index: 88
Number of queues: 8
Rich queuing support: 0 (ifl queued:0)
--------------------------------------------------------------------------------------------
Queue State Max Guaranteed Burst Weight G-Pri E-Pri WRED TAIL
Index Rate Rate Size Rule Rule
88 Configured 10000000000 9500000000 131064 118 GL EL 4 148
89 Configured 10000000000 0 131064 1 GL EL 0 1
90 Configured 10000000000 0 131064 1 GL EL 0 1
91 Configured 10000000000 500000000 131064 6 GL EL 4 72
92 Configured 10000000000 0 131064 1 GL EL 0 1
93 Configured 10000000000 0 131064 1 GL EL 0 1
94 Configured 10000000000 0 131064 1 GL EL 0 1
95 Configured 10000000000 0 131064 1 GL EL 0 1
Note that the scheduler hierarchy does not show ps0.1 under lt-2/0/0, though we have HCOS configured under it and we have TCP on ps0.1 IFL in COS configurations.
This means there is no queues allocated for ps0.1 IFL, since the FPC is not in flexible queueing mode. It operates with limited queues from XMCHIP which has around 32 L1 nodes and hence 256 queues only overall. There is no L4 node available in this mode, where L4 is needed of IFL queueing. In this case, we cannot get IFL scheduling and by default IFL will use IFD-RTP queues.
With flexible-queueing-mode enabled:
lt-2/0/0 178 0 0 0 0
lt-2/0/0-rtp 178 10000000 0 10000000 0
lt-2/0/0.32767 334 0 2000 2000 0
ps0.1 336 100000 0 0 0 ---> IFL scheduler node
NGMPC2(indore vty)# show cos halp ifd 178
rich queueing enabled: 1
Q chip present: 1
IFD name: lt-2/0/0 (Index 178) egress information
XQ chip id: 0 ---> XQ chip enabled.
XQ : chip Scheduler: 0
XQ chip L1 index: 0
XQ chip dummy L2 index: 0
XQ chip dummy L3 index: 0
XQ chip dummy L4 index: 2
XQ chip base Q index: 16
Queue State Max Guaranteed Burst Weight Priorities Drop-Rules Scaling-profile
Index rate rate size G E Wred Tail ID
------ ----------- ----------- ------------ ------- ------ ---------- ---------- ----------------
16 Configured 10000000000 0 67108864 95 GL EL 4 577 3
17 Configured 10000000000 0 67108864 1 GL EL 0 72 3
18 Configured 10000000000 0 67108864 1 GL EL 0 72 3
19 Configured 10000000000 0 67108864 5 GL EL 4 351 3
20 Configured 10000000000 0 67108864 1 GL EL 0 72 3
21 Configured 10000000000 0 67108864 1 GL EL 0 72 3
22 Configured 10000000000 0 67108864 1 GL EL 0 72 3
23 Configured 10000000000 0 67108864 1 GL EL 0 72 3
NGMPC2(indore vty)#
Dedicated queues for PS IFL ps0.1:
NGMPC2(indore vty)# show cos halp ifl 336
IFL type: Stacked
IFL name: (ps0.1) (Index 336)
Underlying IFL name: (lt-2/0/0.32767) (Index 334)
ifl 336 ifd 178 stripped-ifd 178
IFL name: (ps0.1, lt-2/0/0) (Index 336, IFD Index 178) egress information
XQ chip id: 0 ------> XQ chip enabled.
XQ chip Scheduler: 0
XQ chip L2 index: -1
XQ chip L3 index: -1
XQ chip L4 index: 5
XQ chip base Q index: 40
40 Configured 100000000 0 2097152 95 GL EL 4 347 3
41 Configured 100000000 0 2097152 1 GL EL 0 72 3
42 Configured 100000000 0 2097152 1 GL EL 0 72 3
43 Configured 100000000 0 2097152 5 GL EL 4 162 3
44 Configured 100000000 0 2097152 1 GL EL 0 72 3
45 Configured 100000000 0 2097152 1 GL EL 0 72 3
46 Configured 100000000 0 2097152 1 GL EL 0 72 3
47 Configured 100000000 0 2097152 1 GL EL 0 72 3
Therefore as we indicated earlier, we need the flexible-queueing-mode enabled at FPC level, for the HCOS feature to work in LCs like: MPC2E NG PQ & Flex Q (MPC2E-3D-NG) and MPC3E NG PQ & Flex Q. Please apply this configuration and let us know if the issue is resolved.